AT83C51RB2-3CSCM データシートの表示（PDF） - Atmel Corporation

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AT83C51RB2-3CSCM

80C51 High Performance ROM 8-bit Microcontroller

Atmel Corporation 

AT80C51RD2/AT83C51Rx2

Dual Data Pointer

Register

Figure 4. Use of Dual Pointer

The additional data pointer can be used to speed up code execution and reduce code

size.

The dual DPTR structure is a way by which the chip will specify the address of an exter-

nal data memory location. There are two 16-bit DPTR registers that address the external

memory, and a single bit called DPS = AUXR1.0 (see Table 6) that allows the program

code to switch between them (Refer to Figure 4).

External Data Memory

7

0

DPS

AUXR1(A2H)

DPTR1

DPTR0

DPH(83H) DPL(82H)

4113B–8051–03/05

Table 6. AUXR1 Register

AUXR1- Auxiliary Register 1(0A2h)

7

6

5

4

3

2

-

-

-

-

GF3

0

1

0

-

DPS

Bit

Number

7

6

5

4

3

2

1

0

Bit

Mnemonic Description

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

GF3

0

This bit is a general purpose user flag.

Always cleared(1).

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

DPS

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

Reset Value: XXXX XXXX0b

Not bit addressable

Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

13

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