AT83C51RB2-3CSCM データシートの表示（PDF） - Atmel Corporation
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AT83C51RB2-3CSCM Datasheet PDF : 83 Pages
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AT80C51RD2/AT83C51Rx2
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
• Peripheral clock frequency (FCLK PERIPH) ÷ 6
• Peripheral clock frequency (FCLK PERIPH) ÷ 2
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• Rising and/or falling edge capture
• Software timer
• High-speed output
• Pulse width modulator
Module 4 can also be programmed as a Watchdog Timer (see Section "PCA Watchdog
Timer", page 34).
When the compare/capture modules are programmed in the capture mode, software
timer, or high-speed output mode, an interrupt can be generated when the module exe-
cutes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
PCA Component
16-bit Counter
External I/O Pin
P1.2/ECI
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
The PCA timer is a common time base for all five modules (see Figure 8). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 11) and can be programmed to run at:
• 1/6 the peripheral clock frequency (FCLK PERIPH)
• 1/2 the peripheral clock frequency (FCLK PERIPH)
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
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4113B–8051–03/05
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