AT83C51RB2-3CSCM データシートの表示（PDF） - Atmel Corporation

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AT83C51RB2-3CSCM

80C51 High Performance ROM 8-bit Microcontroller

Atmel Corporation 

AT80C51RD2/AT83C51Rx2

Serial I/O Port

The serial I/O port in the T8xc51Rx2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (see Figure 14).

Figure 14. Framing Error Block diagram

SM 0/FE SM 1 SM 2 RE N TB8 RB8 TI

RI S CO N (9 8h )

Se t FE bit if stop bit is 0 (fram ing erro r) (SM OD0 = 1)

SM 0 to UA RT m o de con tro l (SM OD0 = 0 )

SM OD11SM OD0 -

PO F GF1 GF0 PD IDL

To UA RT fra min g e rro r co nt ro l

PCON (87 h)

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (see Table 22) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently, received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (see Figure 15 and Figure 16).

Figure 15. UART Timings in Mode 1

RXD

D0 D1 D2 D3 D4 D5 D6 D7

Start

bit

RI

SMOD0=X

Data byte

Stop

bit

FE

SMOD0=1

35

4113B–8051–03/05

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