AT89C51RC2-3CSCM(2003) データシートの表示（PDF） - Atmel Corporation

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AT89C51RC2-3CSCM
(Rev.:2003)

8-bit Microcontroller with 16K/32K Bytes Flash

Atmel Corporation 

Figure 27. Data Transmission Format (CPHA = 0)

SCK Cycle Number

1

2

3

4

5

6

7

8

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MISO (from Slave)

SS (to Slave)

Capture Point

MSB

bit6

bit5

bit4

bit3

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit2

bit1

LSB

Figure 28. Data Transmission Format (CPHA = 1)

SCK Cycle Number

1

2

3

4

5

6

7

8

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MISO (from Slave)

SS (to Slave)

Capture Point

MSB

bit6

bit5

bit4

bit3

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit2

bit1

LSB

Figure 29. CPHA/SS Timing

MISO/MOSI

Byte 1

Byte 2

Byte 3

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

As shown in Figure 27, the first SCK edge is the MSB capture strobe. Therefore, the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each Byte transmitted (Figure 29).

Figure 28 shows an SPI transmission in which CPHA is ’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 29). This format may be preffered in systems having only one Master and

only one Slave driving the MISO data line.

70 AT89C51RB2/RC2

4180B–8051–04/03

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