AT89C51RC2-3CSCM データシートの表示（PDF） - Atmel Corporation

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AT89C51RC2-3CSCM

8-bit Microcontroller with 16K/32K Bytes Flash

Atmel Corporation 

Warm Reset

Watchdog Reset

AT89C51RB2/RC2

Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)

Oscillator

Start-Up Time

1 ms

VDD Rise Time

10 ms

100 ms

5 ms

820 nF

1.2 µF

12 µF

Note:

20 ms

2.7 µF

3.9 µF

12 µF

These values assume VDD starts from 0V to the nominal value. If the time between 2

on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully

discharged, leading to a bad reset sequence.

To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock

periods is mode independent (X2 or X1).

As detailed in Section “Hardware Watchdog Timer”, page 77, the WDT generates a 96-

clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of

the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ

resistor must be added as shown Figure 33.

Figure 33. Reset Circuitry for WDT Reset-out Usage

VDD

+

VDD

RST

P

VDD

1K

From WDT

Reset Source

To CPU Core

and Peripherals

RST

VSS

VSS

To Other

On-board

Circuitry

81

4180E–8051–10/06

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