ATMEGA64L-8MI データシートの表示（PDF） - Atmel Corporation
部品番号
コンポーネント説明
メーカー
ATMEGA64L-8MI
Atmel Corporation
ATMEGA64L-8MI Datasheet PDF : 363 Pages
| |||
SPI Timing
Characteristics
ATmega64(L)
Table 135. SPI Timing Parameters
Description
Mode
Min
Typ
Max
1
SCK period
Master
See Table 72
2
SCK high/low
Master
50% duty cycle
3
Rise/Fall time
Master
TBD
4
Setup
Master
10
5
Hold
Master
10
6
Out to SCK
Master
7
SCK to out
Master
0.5 • tsck
10
8
SCK to out high
Master
10
9
SS low to out
Slave
15
ns
10
SCK period
Slave
4 • tck
11
SCK high/low(1)
Slave
2 • tck
12
Rise/Fall time
Slave
TBD
13
Setup
Slave
10
14
Hold
Slave
tck
15
SCK to out
Slave
15
16
SCK to SS high
Slave
20
17
SS high to tri-state
Slave
10
18
SS low to SCK
Slave
20
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK >12 MHz
Figure 157. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
45
3
MISO
(Data Input)
MSB
...
7
LSB
8
MOSI
(Data Output)
MSB
...
LSB
2490G–AVR–03/04
331
Share Link: 