Devices
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
XMEGA D4
Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be
performed one page or one byte at a time, while reading the EEPROM is done one byte at a
time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The
most significant bits in the address (E2PAGE) give the page number and the least significant
address bits (E2BYTE) give the byte in the page.
Table 7-3.
EEPROM
size
1K
1K
2K
2K
Number of bytes and pages in the EEPROM.
Page size
E2BYTE
E2PAGE
[bytes]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
No of pages
32
32
64
64
17
8135L–AVR–06/12