C8051F012 データシートの表示（PDF） - Silicon Laboratories

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C8051F012

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

6.2. ADC Modes of Operation

The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before

performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC

conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or

16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate

different system clock speeds.

A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of

Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:

1. Writing a 1 to the ADBUSY bit of ADC0CN;

2. A Timer 3 overflow (i.e. timed continuous conversions);

3. A rising edge detected on the external ADC convert start signal, CNVSTR;

4. A Timer 2 overflow (i.e. timed continuous conversions).

Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.

During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of

ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag. Note: When conversions are

performed “on-demand”, the ADCINT flag, not ADBUSY, should be polled to determine when the

conversion has completed. Converted data is available in the ADC data word MSB and LSB registers, ADC0H,

ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in

Figure 6.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.

The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is

continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different

low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):

1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;

2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;

3. Tracking is active only when the CNVSTR input is low;

4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.

Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the

ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In

this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also

be disabled (shutdown) when the entire chip is in low power standby or sleep modes.

Figure 6.2. 10-Bit ADC Track and Conversion Example Timing

A. ADC Timing for External Trigger Source

CNVSTR

(ADSTM[1:0]=10)

SAR Clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ADCTM=1

ADCTM=0

Low Power or

Convert

Track

Track Or Convert

Convert

Convert

Low Power Mode

Track

B. ADC Timing for Internal Trigger Sources

Timer2, Timer3 Overflow;

Write 1 to ADBUSY

(ADSTM[1:0]=00, 01, 11)

SAR Clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ADCTM=1

Low Power or

Convert

Track

Convert

SAR Clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ADCTM=0 Track or Convert

Convert

Low Power Mode

Track

41

Rev. 1.7

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