C8051F045 データシートの表示（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

CPn+

VIN+

VIN- CPn-

+

CPn

_

OUT

CIRCUIT CONFIGURATION

Positive Hysteresis Voltage

(Programmed with CPnHYP Bits)

VIN-

INPUTS

VIN+

Negative Hysteresis Voltage

(Programmed by CPnHYN Bits)

VOH

OUTPUT

VOL

Positive Hysteresis

Disabled

Negative Hysteresis

Disabled

Maximum

Positive Hysteresis

Maximum

Negative Hysteresis

Figure 11.2. Comparator Hysteresis Plot

The hysteresis of the Comparator is software-programmable via its Comparator Control register (CPT-

nCN). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the

positive and negative-going symmetry of this hysteresis around the threshold voltage.

The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN

(shown in SFR Definition 11.1). The amount of negative hysteresis voltage is determined by the settings of

the CPnHYN bits. As shown in Table 11.1, settings of approximately 20, 10 or 5 mV of negative hysteresis

can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hys-

teresis is determined by the setting the CPnHYP bits.

Comparator interrupts can be generated on either rising-edge and falling-edge output transitions. (For

Interrupt enable and priority control, see Section “12.3. Interrupt Handler” on page 153). The rising and/

or falling -edge interrupts are enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits

(CPnRIE and CPnFIE) in their respective Comparator Mode Selection Register (CPTnMD), shown in SFR

Definition 11.2. These bits allow the user to control which edge (or both) will cause a comparator interrupt.

However, the comparator interrupt must also be enabled in the Extended Interrupt Enable Register (EIE1).

The CPnFIF flag is set to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to

logic 1 upon the Comparator rising-edge interrupt. Once set, these bits remain set until cleared by soft-

ware. The output state of a Comparator can be obtained at any time by reading the CPnOUT bit. A Com-

parator is enabled by setting its respective CPnEN bit to logic 1, and is disabled by clearing this bit to logic

0.Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a com-

parator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up

time” as specified in Table 11.1, “Comparator Electrical Characteristics,” on page 126.

122

Rev. 1.5

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