C8051F045 データシートの表示（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 19.4. SMB0ADR: SMBus0 Address

R/W

SLV6

Bit7

R/W

SLV5

Bit6

R/W

SLV4

Bit5

R/W

SLV3

Bit4

R/W

SLV2

Bit3

R/W

SLV1

Bit2

R/W

SLV0

Bit1

R/W

Reset Value

GC 00000000

Bit0

SFR Address: 0xC3

SFR Page: 0

Bits7-1:

SLV6-SLV0: SMBus0 Slave Address.

These bits are loaded with the 7-bit slave address to which SMBus0 will respond when oper-

ating as a slave transmitter or slave receiver. SLV6 is the most significant bit of the address

and corresponds to the first bit of the address byte received.

Bit0:

GC: General Call Address Enable.

This bit is used to enable general call address (0x00) recognition.

0: General call address is ignored.

1: General call address is recognized.

19.4.5. Status Register

The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 inter-

face. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most

significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at

zero when SI = ‘1’. Therefore, all possible status codes are multiples of eight. This facilitates the use of sta-

tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code

to service the state or jump to a more extensive service routine).

For the purposes of user software, the contents of the SMB0STA register is only defined when the SI flag is

logic 1. Software should never write to the SMB0STA register; doing so will yield indeterminate results. The

28 SMBus0 states, along with their corresponding status codes, are given in Table 19.1.

250

Rev. 1.5

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