C8051F045 データシートの表示（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 4.1. Pin Definitions (Continued)

Name

Pin Numbers

Type Description

F040/2/4/6 F041/3/5/7

P6.4/A12m/A4

76

D I/O Port 6.4. See Port Input/Output section for complete

description.

P6.5/A13m/A5

75

D I/O Port 6.5. See Port Input/Output section for complete

description.

P6.6/A14m/A6

74

D I/O Port 6.6. See Port Input/Output section for complete

description.

P6.7/A15m/A7

73

D I/O Port 6.7. See Port Input/Output section for complete

description.

P7.0/AD0/D0

72

D I/O

Bit 0 External Memory Address/Data bus (Multiplexed

mode)

Bit 0 External Memory Data bus (Non-multiplexed mode)

Port 7.0

See Port Input/Output section for complete description.

P7.1/AD1/D1

71

D I/O Port 7.1. See Port Input/Output section for complete

description.

P7.2/AD2/D2

70

D I/O Port 7.2. See Port Input/Output section for complete

description.

P7.3/AD3/D3

69

D I/O Port 7.3. See Port Input/Output section for complete

description.

P7.4/AD4/D4

68

D I/O Port 7.4. See Port Input/Output section for complete

description.

P7.5/AD5/D5

67

D I/O Port 7.5. See Port Input/Output section for complete

description.

P7.6/AD6/D6

66

D I/O Port 7.6. See Port Input/Output section for complete

description.

P7.7/AD7/D7

65

D I/O Port 7.7. See Port Input/Output section for complete

description.

42

Rev. 1.5

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