C8051F38B-GMR データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

21.6. Function Addressing

The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-

bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new

address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of

the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The

UPDATE bit (FADDR.7) is set to 1 by hardware when software writes a new address to the FADDR regis-

ter. Hardware clears the UPDATE bit when the new address takes effect as described above.

USB Register Definition 21.7. FADDR: USB0 Function Address

Bit

7

6

5

4

3

2

1

0

Name UPDATE

FADDR[6:0]

Type

R

R/W

Reset

0

0

0

0

0

0

0

0

USB Register Address = 0x00

Bit Name

Function

7 UPDATE Function Address Update Bit.

Set to 1 when software writes the FADDR register. USB0 clears this bit to 0 when the

new address takes effect.

0: The last address written to FADDR is in effect.

1: The last address written to FADDR is not yet in effect.

6:0 FADDR[6:0] Function Address Bits.

Holds the 7-bit function address for USB0. This address should be written by software

when the SET_ADDRESS standard device request is received on Endpoint0. The

new address takes effect when the device request completes.

21.7. Function Configuration and Control

The USB register POWER (USB Register Definition 21.8) is used to configure and control USB0 at the

device level (enable/disable, Reset/Suspend/Resume handling, etc.).

USB Reset: The USBRST bit (POWER.3) is set to 1 by hardware when Reset signaling is detected on the

bus. Upon this detection, the following occur:

1. The USB0 Address is reset (FADDR = 0x00).

2. Endpoint FIFOs are flushed.

3. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH).

4. USB register INDEX is reset to 0x00.

5. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared.

6. A USB Reset interrupt is generated if enabled.

Writing a 1 to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to

their default values following this asynchronous reset.

Suspend Mode: With Suspend Detection enabled (SUSEN = 1), USB0 will enter Suspend Mode when

Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = 1). The

Rev. 1.4

183

Share Link: