C8051F38B-GMR データシートの表示（PDF） - Silicon Laboratories

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C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

22. SMBus0 and SMBus1 (I2C Compatible)

The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System

Management Bus Specification, version 1.1, and compatible with the I2C serial bus. The

C8051F380/1/2/3/4/5/6/7/C devices contain two SMBus interfaces, SMBus0 and SMBus1.

Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface auton-

omously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system

clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the

system clock used). A method of extending the clock-low duration is available to accommodate devices

with different speed capabilities on the same bus.

The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The

SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration

logic, and START/STOP control and generation. The SMBus peripherals can be fully driven by software

(i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recogni-

tion and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the

SMBus0 peripheral and the associated SFRs is shown in Figure 22.1. SMBus1 is identical,with the excep-

tion of the available timer options for the clock source, and the timer used to implement the SCL low time-

out feature. Refer to the specific SFR definitions for more details.

SMB0CN

MT S S A A A S

AXT TCRC I

SMAOK B K

TO

RL

ED

QO

RE

S

T

SMB0CF

E I BESSSS

N N U XMMMM

SHSTBBBB

M YHT FCC

B

OOT S S

LEE1 0

D

00

T0 Overflow

01

T1 Overflow (SMBus0) or T5 Overflow (SMBus1)

10

TMR2H Overflow

11

TMR2L Overflow

Interrupt

Request

SMBUS CONTROL LOGIC

Arbitration

SCL Synchronization

SCL Generation (Master Mode)

SDA Control

Hardware Slave Address Recognition

Hardware ACK Generation

IRQ Generation

Data Path

Control

SCL

Control

SDA

Control

FILTER

SCL

N

C

R

O

S

S

B

A

R

Port I/O

SSSSSSSG

L L L L L L LC

VVVVVVV

6543210

SMB0ADR

SSSSSSSE

L L L L L L LH

VVVVVVVA

MMMMMMMC

6543210K

SMB0ADM

SMB0DAT

76543210

FILTER

SDA

N

Figure 22.1. SMBus Block Diagram

Rev. 1.4

205

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