CS4952 データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

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CS4952

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4952/53

System

NTSC-M

PAL-B, D, G, H, I, N

PAL-N (Argentina)

PAL-M

Fsubcarrier

3.5795455 MHz

4.43361875 MHz

3.582056 MHz

3.579611 MHz

Value (dec)

1138817086

1410536854

1139615885

1138838095

Value (hex)

43E0F83E

54131596

43ED288D

43CDDFC7

Table 3. Multi-standard Format FSC Register Configurations

±1350 Hz. It varies per television but in many cases

given an MPEG-2 system clock of 27 MHz

±1350 Hz the resultant color subcarrier produced

will be outside of the televisions ability to compen-

sate and the chrominance information will not be

displayed (black and white picture only).

The CS4952/3 is designed to provide automatic

compensation for an excessively inaccurate

MPEG-2 system clock. Sub-carrier compensation

is enabled through the XTAL bit of the

CONTROL_2 register. When enabled the

CS4952/3 will utilize a common quartz color burst

crystal (3.579545 MHz ±50 ppm for NTSC) at-

tached to the ADDR and XTAL pins to automati-

cally compare and compensate the color subcarrier

synthesis process. Use of the ADDR and XTAL

pins requires that the host interface is configured

for I2C operation.

Closed Caption Insertion

The CS4952/3 is capable of NTSC Closed Caption

insertion on lines 21 and 284 independently.

Closed captioning is enabled for either or both lines

21 & 284 via the CC_EN [1:0] register bits and data

to be inserted is also written into the four Closed

Caption Data registers. The CS4952/3 when en-

abled automatically generates the seven cycles of

clock run-in (32 x line rate), start bit insertion

(001)and finally insertion of the two data bytes per

line. Data low at the video outputs corresponds to 0

IRE and data high corresponds to 50 IRE.

There are two independent 8-bit registers per line

(CC_21_1 & CC_21_2 for line 21 and CC_284_1

& CC_284_2 for line 284). Interrupts are also pro-

vided to simplify the handshake between the driver

software and the chip. Typically the host would

write all 4 bytes to be inserted into the registers and

then enable closed caption insertion and interrupts.

As the closed caption interrupts occur the host soft-

ware would respond by writing the next two bytes

to be inserted to the correct control registers and

then clear the interrupt and wait for the next field.

Color Bar Generator

The CS4952/3 is equipped with a color bar genera-

tor that is enabled through the CBAR bit of the

CONTROL_1 register. The color bar generator

works in Master or Slave Mode and has no effect

on the video input/output timing. If the CS4952/3 is

configured for Slave Mode color bars, proper video

timing must be present on the HSYNC and

VSYNC pins for the color bars to be displayed.

Given proper Slave Mode input timing or Master

Mode, the color bar generator will override the vid-

eo input pixel data.

The output of the color bar generator is instantiated

after the chroma interpolation filter and before the

luma delay line. The generated color bar numbers

are for 100% amplitude, 100% saturation NTSC

EIA color bars or 100% amplitude, 100% satura-

tion PAL EBU color bars. For PAL color bars, the

CS4952/3 generates NTSC color bar values, which

are very close to standard PAL values. The exact

luma and chroma values are listed in Table 4.

DS223PP2

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