JS28F320J3C-115 データシートの表示（PDF） - Intel
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JS28F320J3C-115 Datasheet PDF : 72 Pages
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256-Mbit J3 (x8/x16)
9.2
Device Commands
When the VPEN voltage ≤ VPENLK, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,
and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI. Table 14, “Command Bus-Cycle Definitions” on page 35 defines these
commands.
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Command
Read Array
Read Identifier Codes
Read Query
Read Status Register
Clear Status Register
Write to Buffer
Word/Byte Program
Block Erase
Block Erase, Program
Suspend
Block Erase, Program
Resume
Configuration
Set Block Lock-Bit
Scalable or
Basic
Command
Set(2)
Bus
Cycles
Req’d.
First Bus Cycle
Oper(3) Addr(4) Data(5,6)
SCS/BCS
1
Write
X
0xFF
SCS/BCS
≥2
Write
X
0X90
SCS
≥2
Write
X
0x98
SCS/BCS
2
Write
X
0x70
SCS/BCS
1
Write
X
0x50
SCS/BCS
>2
Write
BA
0xE8
SCS/BCS
2
SCS/BCS
2
Write
Write
X
0x40 or
0x10
BA
0x20
SCS/BCS
1
Write
X
0xB0
SCS/BCS
1
Write
X
0xD0
SCS
SCS
2
Write
X
0xB8
2
Write
X
0x60
Second Bus Cycle
Oper(3) Addr(4) Data(5,6)
Notes
1
Read
IA
ID
1,7
Read
QA
QD
1
Read
X
SRD
1,8
1
Write
BA
N
1,9, 10,
11
Write
PA
PD 1,12,13
Write
BA
0xD0 1,11,12
1,12,14
1,12
Write
X
CC
1
Write
BA
0x01
1
Datasheet
35
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