JS28F320J3C-115 データシートの表示（PDF） - Intel
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JS28F320J3C-115 Datasheet PDF : 72 Pages
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256-Mbit J3 (x8/x16)
Figure 24. Set Block Lock-Bit Flowchart
Start
Write 60H,
Block Address
Write 01H,
Block Address
Read Status Register
0
SR.7 =
1
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
Voltage Range Error
0
SR.4,5 =
0
SR.4 =
0
Set Lock-Bit
Successful
1
Command Sequence
Error
1
Set Lock-Bit Error
Bus
Operation
Write
Write
Command
Comments
Set Block Lock-Bit Data = 60H
Setup
Addr =Block Address
Set Block Lock-Bit Data = 01H
Confirm
Addr = Block Address
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in read
array mode.
Bus
Operation
Standby
Standby
Standby
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.4
1 = Set Lock-Bit Error
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
command, in cases where multiple lock-bits are set before full status is
checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Datasheet
65
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