LC4032C-75T44BSES データシートの表示（PDF） - Lattice Semiconductor

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LC4032C-75T44BSES

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description1, 2, 3

Min. Max. Min. Max. Min. Max. Units

tPD

tPD_MC

tS

tST

tSIR

tSIRZ

tH

tHT

tHIR

tHIRZ

5-PT bypass combinatorial propagation delay

— 5.0 — 7.5 — 10.0 ns

20-PT combinatorial propagation delay through macrocell — 5.5 — 8.0 — 10.5 ns

GLB register setup time before clock

3.0 — 4.5 — 5.5 — ns

GLB register setup time before clock with T-type register 3.2 — 4.7 — 5.5 — ns

GLB register setup time before clock, input register path 1.2 — 1.7 — 1.7 — ns

GLB register setup time before clock with zero hold

2.2 — 2.7 — 2.7 — ns

GLB register hold time after clock

0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock with T-type register

0.0 — 0.0 — 0.0 — ns

GLB register hold time after clock, input register path

1.0 — 1.0 — 1.0 — ns

GLB register hold time after clock, input register path with

zero hold

0.0

—

0.0

—

0.0

—

ns

tCO

GLB register clock-to-output delay

— 3.4 — 4.5 — 6.0 ns

tR

External reset pin to output delay

— 6.3 — 9.0 — 10.5 ns

tRW

External reset pulse duration

2.0 — 4.0 — 4.0 — ns

tPTOE/DIS Input to output local product term output enable/disable — 7.0 — 9.0 — 10.5 ns

tGPTOE/DIS Input to output global product term output enable/disable — 9.0 — 10.3 — 12.0 ns

tGOE/DIS Global OE input to output enable/disable

— 5.0 — 7.0 — 8.0 ns

tCW

Global clock width, high or low

2.2 — 3.3 — 4.0 — ns

tGW

Global gate width low (for low transparent) or high (for

high transparent)

2.2 — 3.3 — 4.0 — ns

tWIR

Input register clock width, high or low

2.2 — 3.3 — 4.0

fMAX4

Clock frequency with internal feedback

227 — 168 — 125

fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)]

156 — 111 — 86

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

— ns

— MHz

— MHz

Timing v.3.2

23

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