ST92250JDV2TC データシートの表示（PDF） - STMicroelectronics

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ST92250JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

EXTERNAL INPUT CONTROL

(T_ICR)

R250 - Read/Write

Register Page: 10

Reset value: 0000 0000 (00h)

REGISTER

7

0

IN3 IN2 IN1 IN0 A0 A1 B0 B1

Bits 1:0 = B[0:1]: TxINB Pin event.

These bits are set and cleared by software.

B0

B1

TxINB Pin Event

0

0

No operation

0

1

Falling edge sensitive

1

0

Rising edge sensitive

1

1

Rising and falling edges

Bits 7:4 = IN[3:0]: Input pin function.

These bits are set and cleared by software.

IN[3:0] bits

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

TxINA

Pin Function

not used

not used

Gate

Gate

not used

Trigger

Gate

Trigger

Clock Up

Up/Down

Trigger Up

Up/Down

Autodiscr.

Trigger

Ext. Clock

Trigger

TxINB Input

Pin Function

not used

Trigger

not used

Trigger

Ext. Clock

not used

Ext. Clock

Trigger

Clock Down

Ext. Clock

Trigger Down

not used

Autodiscr.

Ext. Clock

Trigger

Gate

Bits 3:2 = A[0:1]: TxINA Pin event.

These bits are set and cleared by software.

A0

A1

TxINA Pin Event

0

0

No operation

0

1

Falling edge sensitive

1

0

Rising edge sensitive

1

1

Rising and falling edges

PRESCALER REGISTER (PRSR)

R251 - Read/Write

Register Page: 10

Reset value: 0000 0000 (00h)

7

0

P7 P6 P5 P4 P3 P2 P1 P0

This register holds the preset value for the 8-bit

prescaler. The PRSR content may be modified at

any time, but it will be loaded into the prescaler at

the following prescaler underflow, or as a conse-

quence of a counter reload (either by software or

upon external request).

Following a RESET condition, the prescaler is au-

tomatically loaded with 00h, so that the prescaler

divides by 1 and the maximum counter clock is

generated (Crystal oscillator clock frequency divid-

ed by 6 when MODER.5 = DIV2 bit is set).

The binary value programmed in the PRSR regis-

ter is equal to the divider value minus one. For ex-

ample, loading PRSR with 24 causes the prescal-

er to divide by 25.

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