LTC2209IUP-TR(RevA) データシートの表示（PDF） - Linear Technology

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LTC2209IUP-TR
(Rev.:RevA)

16-Bit, 160Msps ADC

Linear Technology 

LTC2209

BLOCK DIAGRAM

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

DITHER

SIGNAL

GENERATOR

SENSE

VCM

RANGE

SELECT

PGA

BUFFER

VOLTAGE

REFERENCE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

ADC CLOCKS

ADC

REFERENCE

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

CONTROL

LOGIC

ENC+ ENC–

SHDN PGA RAND M0DE LVDS DITH

VDD

FIFTH PIPELINED

ADC STAGE

GND

CORRECTION LOGIC

AND

SHIFT REGISTER

OUTPUT

DRIVERS

OVDD

CLKOUT+

CLKOUT–

OF+

OF–

D15+

• D15–

•

• D0+

D0–

OGND

2209 F01

Figure 1. Functional Block Diagram

2209fa

16

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