M25PE80-VMN6TP データシートの表示（PDF） - STMicroelectronics

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M25PE80-VMN6TP

8 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

Instructions

Figure 7. Write Enable (WREN) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

M25PE80

6.2

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

● Power-up

● Write Disable (WRDI) instruction completion

● Page Write (PW) instruction completion

● Page Program (PP) instruction completion

● Write to Lock Register (WRLR) instruction completion

● Page Erase (PE) instruction completion

● Sector Erase (SE) instruction completion

● Bulk Erase (BE) instruction completion

Figure 8. Write Disable (WRDI) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

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