ST72521M7 データシートの表示（PDF） - STMicroelectronics

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ST72521M7

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 Clock Security System (CSS)

Symbol

Parameter

fSFOSC

Safe Oscillator Frequency 1)

Note:

1. Data based on characterization results.

Conditions

Min

Typ

Max

Unit

3

MHz

12.5.6 PLL Characteristics

Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C1) or VDD 4.5 to 5.5V @ TA -40 to 125°C

Symbol

Parameter

VDD(PLL)

PLL Operating Range

fOSC

PLL input frequency range

fCPU/∆ fCPU Instantaneous PLL jitter 1)

Conditions

TA 0 to 70°C

TA -40 to +125°C

fOSC = 4 MHz.

fOSC = 2 MHz.

Min

Typ

Max

3.8

5.5

4.5

5.5

2

4

1.0

2.5

2.5

4.0

Unit

V

MHz

%

%

Note:

1. Data characterized but not tested.

Figure 88. PLL Jitter vs. Signal frequency1

0.8

0.7

0.6

PLL ON

0.5

PLL OFF

0.4

0.3

0.2

0.1

0

2000

1000

500

250

125

Application Signal Frequency (KHz)

The user must take the PLL jitter into account in

the application (for example in serial communica-

tion or sampling of high frequency signals). The

PLL jitter is a periodic effect, which is integrated

over several CPU cycles. Therefore the longer the

period of the application signal, the less it will be

impacted by the PLL jitter.

Figure 88 shows the PLL jitter integrated on appli-

cation signals in the range 125kHz to 2MHz. At fre-

quencies of less than 125KHz, the jitter is negligi-

ble.

Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C

168/199

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