PIC12HV609-I/SN データシートの表示（PDF） - Microchip Technology
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PIC12HV609-I/SN Datasheet PDF : 212 Pages
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PIC12F609/615/617/12HV609/615
5.2.4.3
GP2/AN2(1)/T0CKI/INT/COUT/
CCP1(1)/P1A(1)
Figure 5-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC(1)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from Comparator
• a Capture input/Compare input/PWM output(1)
• a PWM output(1)
Note 1: PIC12F615/617/HV615 only.
FIGURE 5-2:
BLOCK DIAGRAM OF GP2
Data Bus
WR
WPU
RD
WPU
DQ
CK Q
WR
GPIO
DQ
CK Q
C1OE
Enable
Analog(1)
Input Mode
GPPU
VDD
Weak
C1OE 1
0
VDD
I/O Pin
VSS
WR
TRISIO
DQ
CK Q
RD
TRISIO
RD
GPIO
WR
IOC
RD
IOC
DQ
CK Q
Analog(1)
Input Mode
QD
EN
Q1
QD
Interrupt-on-
Change
Q S(2)
R
Write ‘0’ to GBIF
From other
GP<5:3, 1:0> pins
EN
RD GPIO
To Timer0
To INT
To A/D Converter(3)
Note 1:
2:
3:
Comparator mode and ANSEL determines Analog Input mode.
Set has priority over Reset.
PIC12F615/617/HV615 only.
DS41302D-page 48
2010 Microchip Technology Inc.
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