PIC12F1822T-I/SL データシートの表示（PDF） - Microchip Technology

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PIC12F1822T-I/SL

8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC12F/LF1822/16F/LF1823

24.6.4 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSP1CON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSP1ADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSP1STAT1

register to be set. Following this, the Baud Rate Gen-

erator is reloaded with the contents of SSP1ADD<7:0>

and resumes its count. When the Baud Rate Genera-

tor times out (TBRG), the SEN bit of the SSP1CON2

FIGURE 24-26: FIRST START BIT TIMING

register will be automatically cleared by hardware; the

Baud Rate Generator is suspended, leaving the SDA

line held low and the Start condition is complete.

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCL1IF, is set, the Start condition is

aborted and the I2C module is reset into its

Idle state.

2: The Philips I2C Specification states that a

bus collision cannot occur on a Start.

Write to SEN bit occurs here

Set S bit (SSP1STAT<3>)

SDA = 1,

SCL = 1

TBRG

TBRG

At completion of Start bit,

hardware clears SEN bit

and sets SSP1IF bit

Write to SSP1BUF occurs here

SDA

1st bit

2nd bit

SCL

TBRG

S

TBRG

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 259

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