PIC16LF1512-I/SP データシートの表示（PDF） - Microchip Technology

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PIC16LF1512-I/SP

28-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

PIC16(L)F1512/3

7.6.3 PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 7-3.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

U-0

U-0

U-0

R/W-0/0

U-0

U-0

OSFIE

—

—

—

BCLIE

—

—

bit 7

R/W-0/0

CCP2IE

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6-4

bit 3

bit 2-1

bit 0

OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt

0 = Disables the oscillator fail interrupt

Unimplemented: Read as ‘0’

BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP bus collision interrupt

0 = Disables the MSSP bus collision interrupt

Unimplemented: Read as ‘0’

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

 2012-2014 Microchip Technology Inc.

DS40001624C-page 71

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