PIC18F2455T-I/PT データシートの表示（PDF） - Microchip Technology

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PIC18F2455T-I/PT

28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F2455/2550/4455/4550

TABLE 28-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

102 TR

SDA and SCL

Rise Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

1000

300

300

ns CB is specified to be from

ns 10 to 400 pF

ns

103 TF

SDA and SCL

Fall Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

300 ns CB is specified to be from

300 ns 10 to 400 pF

100 ns

90

TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms Repeated Start

ms condition

91

THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

Hold Time

400 kHz mode 2(TOSC)(BRG + 1) —

ms clock pulse is generated

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

106 THD:DAT Data Input

100 kHz mode

0

—

ns

Hold Time

400 kHz mode

0

0.9 ms

107 TSU:DAT Data Input

100 kHz mode

250

Setup Time

400 kHz mode

100

—

ns (Note 2)

—

ns

92

TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

109 TAA

Output Valid

from Clock

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

3500 ns

—

1000 ns

—

—

ns

110 TBUF Bus Free Time 100 kHz mode

4.7

— ms Time the bus must be free

400 kHz mode

1.3

—

ms before a new transmission

can start

D102 CB

Bus Capacitive Loading

—

400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCL line is released.

DS39632E-page 400

© 2009 Microchip Technology Inc.

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