PIC18LF45J10T-I/SP データシートの表示（PDF） - Microchip Technology

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PIC18LF45J10T-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

FIGURE 16-4:

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

ASYNCHRONOUS TRANSMISSION

Word 1

Start bit

bit 0

1 TCY

bit 1

Word 1

Word 1

Transmit Shift Reg

bit 7/8 Stop bit

FIGURE 16-5:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Word 2

1 TCY

Start bit

bit 0

Word 1

Transmit Shift Reg.

1 TCY

bit 1

Word 1

bit 7/8 Stop bit

Start bit

bit 0

Word 2

Word 2

Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

PIR1

PIE1

IPR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

43

PSPIF(1) ADIF

RCIF

TXIF SSP1IF CCP1IF TMR2IF TMR1IF 45

PSPIE(1) ADIE

RCIE

TXIE SSP1IE CCP1IE TMR2IE TMR1IE 45

PSPIP(1) ADIP

RCIP

TXIP SSP1IP CCP1IP TMR2IP TMR1IP 45

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D

45

TXREG

EUSART Transmit Register

45

TXSTA

CSRC

TX9

TXEN SYNC SENDB BRGH TRMT TX9D

45

BAUDCON ABDOVF RCIDL

—

SCKP BRG16

—

WUE ABDEN

45

SPBRGH EUSART Baud Rate Generator Register High Byte

45

SPBRG

EUSART Baud Rate Generator Register Low Byte

45

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

DS39682C-page 198

Preliminary

© 2007 Microchip Technology Inc.

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