PIC18F24J10T-L/SP データシートの表示（PDF） - Microchip Technology

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PIC18F24J10T-L/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

BCF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Bit Clear f

BCF f, b {,a}

0 ≤ f ≤ 255

0≤b≤7

a ∈ [0,1]

0 → f<b>

None

1001 bbba ffff ffff

Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write

register ‘f’

Example:

BCF

Before Instruction

FLAG_REG =

After Instruction

FLAG_REG =

FLAG_REG, 7, 0

C7h

47h

BN

Branch if Negative

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

If Jump:

Q1

Decode

No

operation

If No Jump:

Q1

Decode

BN n

-128 ≤ n ≤ 127

if Negative bit is ‘1’

(PC) + 2 + 2n → PC

None

1110 0110 nnnn nnnn

If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

1

1(2)

Q2

Read literal

‘n’

No

operation

Q3

Process

Data

No

operation

Q4

Write to PC

No

operation

Q2

Read literal

‘n’

Q3

Process

Data

Q4

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

If Negative =

PC

=

If Negative =

PC

=

BN Jump

address (HERE)

1;

address (Jump)

0;

address (HERE + 2)

DS39682C-page 250

Preliminary

© 2007 Microchip Technology Inc.

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