PIC18F45J50-I/SOSQTP データシートの表示（PDF） - Microchip Technology

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PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

FIGURE 20-6:

EUSARTx RECEIVE BLOCK DIAGRAM

BRG16

x64 Baud Rate CLK

SPBRGHx SPBRGx

Baud Rate Generator

CREN

 64

or

 16

or

4

OERR

FERR

MSb

Stop (8)

RSR Register

7  1

LSb

0 Start

RX9

Pin Buffer

and Control

Data

Recovery

RXx

{ RX9D

RCREGx Register

2-Entry FIFO

SPEN

RXDTP

Unread Data

in FIFO

8

Interrupt

RCxIF

RCxIE

Data Bus

FIGURE 20-7:

RXx (pin)

Rcv Shift Reg

Rcv Buffer Reg

Read Rcv

Buffer Reg

RCREGx

RCxIF

(Interrupt Flag)

OERR bit

CREN

ASYNCHRONOUS RECEPTION

Start

bit bit 0 bit 1

bit 7/8 Stop

bit

Start

bit

bit 0

Word 1

RCREGx

Start

bit 7/8 Stop bit

bit

Word 2

RCREGx

bit 7/8 Stop

bit

Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after

the third word, causing the OERR (Overrun) bit to be set.

 2011 Microchip Technology Inc.

DS39931D-page 337

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