PIC18F66K22-I/PTRSL データシートの表示（PDF） - Microchip Technology

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PIC18F66K22-I/PTRSL

64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

Microchip Technology 

PIC18F87K22 FAMILY

TABLE 31-24: MSSP I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100 THIGH Clock High

100 kHz mode 2(TOSC)(BRG + 1) —

—

Time

400 kHz mode 2(TOSC)(BRG + 1) —

—

1 MHz mode(1) 2(TOSC)(BRG + 1) —

—

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) —

—

400 kHz mode 2(TOSC)(BRG + 1) —

—

1 MHz mode(1) 2(TOSC)(BRG + 1) —

—

102 TR

SDAx and

SCLx Rise

Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

1000

300

300

ns CB is specified to be from

ns 10 to 400 pF

ns

103 TF

SDAx and

100 kHz mode

SCLx Fall Time 400 kHz mode

—

20 + 0.1 CB

300 ns CB is specified to be from

300 ns 10 to 400 pF

1 MHz mode(1)

—

100 ns

90

TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —

— Only relevant for Repeated

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) —

— Start condition

1 MHz mode(1) 2(TOSC)(BRG + 1) —

—

91

THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —

— After this period, the first

Hold Time

400 kHz mode 2(TOSC)(BRG + 1) —

— clock pulse is generated

1 MHz mode(1) 2(TOSC)(BRG + 1) —

—

106 THD:DAT Data Input

100 kHz mode

0

Hold Time

400 kHz mode

0

—

ns

0.9 s

1 MHz mode(1)

—

—

ns

107 TSU:DAT Data Input

100 kHz mode

250

Setup Time

400 kHz mode

100

—

ns (Note 2)

—

ns

1 MHz mode(1)

—

—

ns

92

TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —

—

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) —

—

1 MHz mode(1) 2(TOSC)(BRG + 1) —

—

109 TAA

Output Valid 100 kHz mode

—

3500 ns

from Clock

400 kHz mode

—

1000 ns

1 MHz mode(1)

—

—

ns

110 TBUF Bus Free Time 100 kHz mode

4.7

400 kHz mode

1.3

1 MHz mode(1)

—

—

s Time the bus must be free

—

s before a new transmission

—

s can start

D102 CB

Bus Capacitive Loading

—

400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107  250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit

to the SDAx line, Parameter #102 + Parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCLx line is released.

 2011 Microchip Technology Inc.

DS39960D-page 521

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