PIC18LF448T-I/SP データシートの表示（PDF） - Microchip Technology
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PIC18LF448T-I/SP
Microchip Technology
PIC18LF448T-I/SP Datasheet PDF : 402 Pages
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PIC18FXX8
FIGURE 27-13: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
78
79
79
78
Bit 6 - - - - - -1
LSb
SDI
MSb In
74
73
Note: Refer to Figure 27-5 for load conditions.
75, 76
Bit 6 - - - -1
LSb In
TABLE 27-13: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 —
of Byte 2
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75
TdoR
SDO Data Output Rise Time PIC18FXX8
—
25
PIC18LFXX8
—
45
76
TdoF
SDO Data Output Fall Time
—
25
78
TscR
SCK Output Rise Time
(Master mode)
PIC18FXX8
PIC18LFXX8
—
25
—
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after PIC18FXX8
TscL2doV SCK Edge
PIC18LFXX8
—
50
—
100
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
© 2006 Microchip Technology Inc.
DS41159E-page 349
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