PSD4235G2V-C-70M データシートの表示（PDF） - STMicroelectronics

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PSD4235G2V-C-70M

Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply

STMicroelectronics 

PSD9XX Family

The

PSD935G2

Functional

Blocks

(cont.)

PSD935G2

Table 15. 80C251 Configurations

Configuration

80C251

Read/Write

Pins

Connecting to

PSD935G2

Pins

Page Mode

WR

1

RD

PSEN

CNTL0

CNTL1

CNTL2

Non-Page Mode, 80C31 compatible

A[7:0] multiplex with D[7:0}

2

WR

PSEN only

CNTL0

CNTL1

Non-Page Mode

A[7:0] multiplex with D[7:0}

3

WR

PSEN only

CNTL0

CNTL1

Page Mode

A[15:8] multiplex with D[7:0}

4

WR

RD

PSEN

CNTL0

CNTL1

CNTL2

Page Mode

A[15:8] multiplex with D[7:0}

9.3.3.3 80C51XA

The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that

can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are

multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed

with data bits D[7:0].

The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 18).

The 80C51XA improves bus throughput and performance by executing Burst cycles for

code fetches. In Burst Mode, address A19-4 are latched internally by the PSD935G2, while

the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access

time is then measured from address A3-A0 valid to data in valid. The PSD bus timing

requirement in Burst Mode is identical to the normal bus cycle, except the address setup

and hold time with respect to ALE does not apply.

9.3.3.4 68HC11

Figure 19 shows an interface to a 68HC11 where the PSD935G2 is configured in 8-bit

multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR

signals for external devices.

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