ZPSD5XX データシートの表示（PDF） - STMicroelectronics

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ZPSD5XX

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

System

Configuration

(Cont.)

PSD5XX Family

Table 33. Other Register Function

Register Name

Register Function

PAGE REGISTER

INTR. READ

CLEAR

INTR.

EDGE/LEVEL

INTR. MASK

INTR.

REQUEST LATCH

INTR.

PRIORITY STATUS

VM

PMMR0

PMMR1

STATUS FLAGS

GLOBAL

COMMAND

DLCY

SOFTWARE

LOAD/STORE

FREEZE

COMMAND

CMD3 – 0

CNTR3 – 0

IMG3 – 0

A 4-bit register that supports paging.

Reading this register clears all the pending edge sensitive

interrupts.

Define interrupt input as level or edge sensitive.

Mask selected interrupt input.

A “1” in the register indicates the corresponding interrupt is

pending.

The register indicates which pending interrupt has the highest

priority.

1. Configures the PSD SRAM to be accessed by “PSEN” as

program space (8031 design).

2. Enable the Peripheral I/O Mode of Port A.

Power management registers; enable the PSD Power Down Mode

and other power saving configurations.

Counter/Timer Freeze Acknowledge bits.

Specifies the Counter/Timer operation mode; and to start or stop

the Counter/Timers.

Specifies the delay cycles to the Counter/Timers.

This register enables a load (to the Counter/Timer) or store

(in the Image Register) operation.

This register disables the timer state-machine before access to the

Image Register is allowed.

Command Registers for the configuration of the Counter/Timers.

The four 16-bit Counter/Timers.

The Image Registers for CNTR3 – 0.

107

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