PSD511B1-C-90UI データシートの表示（PDF） - STMicroelectronics
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PSD511B1-C-90UI Datasheet PDF : 153 Pages
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PSD5XX Family
AC/DC Parameters – ZPLD Timing Parameters
(ZPSD5XXV Versions)
Counter/Timer Timing (3.0 V ± 10%)
Symbol
fMAX
t CHCL
t CLCH
t CHPV
t CHPV1
t LVCH
t MIN
Parameter
Maximum Frequency
Clock High Time
Clock Low Time
Clock to Output Delay
Clock to Watchdog Output Delay
Input Setup Time Relative
to Rising Level Clock
Minimum Clock Period
Conditions
Any Input
1/fMAX
-20
-25
ZPLD_TURBO
Min Max Min Max
OFF*
20.00
12.50
16
22
16
22
50
55
90
100
45
60
50
80
0
0
0
0
Add 20
Add 20
(Note 2)
0
Unit
MHz
ns
ns
ns
ns
ns
ns
Interrupt Timing (3.0 V ± 10%)
Symbol
Parameter
-20
-25
ZPLD_TURBO
Conditions Min Max Min Max
OFF*
Unit
t IVIV
Interrupt Request Input to
Interrupt Output
(Note 3)
70
120
0
ns
t RXIX
Read Vector to Interrupt
Request Clear
60
100
0
ns
t ILIL
Interrupt Request Minimum
Pulse Width
40
45
0
ns
t RLQV
RD to Data Valid Interrupt
Controller
(Note 1)
50
90
0
ns
NOTES: 1. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS, LDS,
UDS signals.
2. For inputs which use PPLD only.
3. This timing is only valid when read to the interrupt request latch and priority status latch are not valid.
*If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
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