ST92P141K4D6/XXX データシートの表示（PDF） - STMicroelectronics

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ST92P141K4D6/XXX

8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL

STMicroelectronics 

ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)

5.4 CLOCK CONTROL REGISTERS

MODE REGISTER (MODER)

R235 - Read/Write

System Register

Reset Value: 1110 0000 (E0h)

7

0

-

- DIV2 PRS2 PRS1 PRS0 -

-

*Note: This register contains bits which relate to

other functions; these are described in the chapter

dealing with Device Architecture. Only those bits

relating to Clock functions are described here.

Bit 5 = DIV2: OSCIN Divided by 2.

This bit controls the divide by 2 circuit which oper-

ates on the OSCIN Clock.

0: No division of the OSCIN Clock

1: OSCIN clock is internally divided by 2

CLOCK CONTROL REGISTER (CLKCTL)

R240 - Read Write

Register Page: 55

Reset Value: 0000 0000 (00h)

7

0

INT_SEL - - - SRESEN CKAF_SEL WFI_CKSEL LPOWFI

Bit 7 = INT_SEL: Interrupt Selection.

0: Select the external interrupt pin as interrupt

source (Reset state)

1: Select the internal RCCU interrupt (see Section

5.3.5)

Bit 4:6 = Reserved.

Must be kept reset for normal operation.

Bit 4:2 = PRS[2:0]: Clock Prescaling.

These bits define the prescaler value used to pres-

cale CPUCLK from INTCLK. When these three

bits are reset, the CPUCLK is not prescaled, and is

equal to INTCLK; in all other cases, the internal

clock is prescaled by the value of these three bits

plus one.

Bit 3 = SRESEN: Software Reset Enable.

0: The HALT instruction turns off the quartz, the

PLL and the CCU

1: A Reset is generated when HALT is executed

Bit 2 = CKAF_SEL: Alternate Function Clock Se-

lect.

0: CK_AF clock not selected

1: Select CK_AF clock

Note: To check if the selection has actually oc-

curred, check that CKAF_ST is set. If no clock is

present on the CK_AF pin, the selection will not

occur.

Bit 1 = WFI_CKSEL: WFI Clock Select.

This bit selects the clock used during Low power

WFI mode if LPOWFI = 1.

0: INTCLK during WFI is CLOCK2/16

1: INTCLK during WFI is CK_AF, further divided

by 16, providing it is present. In effect this bit

sets CKAF_SEL in WFI mode

WARNING: When the CK_AF is selected as Low

Power WFI clock but the XTAL is not turned off

(R242.4 = 0), after exiting from the WFI, CK_AF

will be still selected as system clock. In this case,

reset the R240.2 bit to switch back to the XT.

Bit 0 = LPOWFI: Low Power mode during Wait For

Interrupt.

0: Low Power mode during WFI disabled. When

WFI is executed, the CPUCLK is stopped and

INTCLK is unchanged

1: The ST9 enters Low Power mode when the WFI

instruction is executed. The clock during this

state depends on WFI_CKSEL

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