ST92T163R4D0 データシートの表示（PDF） - STMicroelectronics

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ST92T163R4D0

8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

STMicroelectronics 

ST92163 - EXTERNAL MEMORY INTERFACE (EXTMI)

EXTERNAL MEMORY SIGNALS (Cont’d)

6.2.4 RW: Read/Write

The behavior of this signal is affected by the MC,

RW (Alternate Function Output, Active low,

Tristate) identifies the type of memory cycle:

ETO and BSZ bits in the EMR1 register. Refer to

the Register description.

RW=”1” identifies a memory read cycle, RW=”0” 6.2.5 BREQ, BACK: Bus Request, Bus

identifies a memory write cycle. It is defined at the Acknowledge

beginning of each memory cycle and it remains

stable until the following memory cycle. RW is re-

leased in high-impedance during bus acknowl-

edge cycle or under processor control by setting

the HIMP bit (MODER). RW is enabled via soft-

ware as the Alternate Function output of the asso-

ciated I/O port bit (refer to specific ST9 device to

identify the port and pin). Under Reset status, the

associated bit of the port is set into bidirectional

Note: These pins are available only on some ST9

devices (see Pin description).

BREQ (Alternate Function Input, Active low) indi-

cates to the ST9 that a bus request has tried or is

trying to gain control of the memory bus. Once en-

abled by setting the BRQEN bit (MODER.1,

R235), BREQ is sampled with the falling edge of

the processor internal clock during phase T2.

weak pull-up mode.

n

n

Figure 52. External memory Read/Write sequence with external wait (WAIT pin)

n

T1

T2

T1

T2

T1

T2

WAI T

SYST EM

CLOCK

P1

AS (MC=0)

ALE (MC=1)

DS (MC=0)

MULTIPLEXED

P0

RW (MC=0)

DS (MC=1)

RW (MC=1)

MULTIPLEXED

P0

RW (MC=0)

DS (MC=1)

RW (MC=1)

ADDRESS

ADD.

D.IN

ADD. D.OUT

ADDRESS

ADDRESS

ADDRESS

D.IN

ADD.

D.IN

ADDRESS

D.OUT ADD.

DATA OUT

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