PSD811G3V-B-20UI データシートの表示（PDF） - STMicroelectronics
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PSD811G3V-B-20UI Datasheet PDF : 110 Pages
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PSD835G2
PSD8XX Family
PSD835G2 AC/DC Parameters – CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
GPLD Combinatorial Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
-90
-12
Slew
PT TURBO Rate
Min Max Min Max Aloc OFF (Note 1) Unit
t PD
GPLD Input Pin/Feedback to
GPLD Combinatorial Output
38
43 Add 4 Add 20 Sub 6 ns
t EA
GPLD Input to GPLD Output
Enable
43
45
Add 20 Sub 6 ns
t ER
GPLD Input to GPLD Output
Disable
43
45
Add 20 Sub 6 ns
t ARP
GPLD Register Clear or
Preset Delay
38
43
Add 20 Sub 6 ns
t ARPW
GPLD Register Clear or
Preset Pulse Width
28
30
Add 20
ns
tARD GPLD Array Delay
Any Micro⇔Cell
23
27 Add 4
ns
NOTE: 1. Fast Slew Rate output available on Port C and F.
GPLD Micro⇔Cell Synchronous Clock Mode Timing (3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
-90
-12
Slew
PT TURBO Rate
Min Max Min Max Aloc OFF (Note 1) Unit
fMAX
tS
tH
t CH
t CL
t CO
t ARD
t MIN
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback ( fCNT)
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
GPLD Array Delay
Minimum Clock Period
1/(tS + t CO )
24.3
20.4
MHz
1/(tS + t CO –10)
32.2
25.6
MHz
1/(tCH + t CL)
45.0
35.7
MHz
18
23
Add 4 Add 20
ns
0
0
ns
Clock Input 11
14
ns
Clock Input 11
14
ns
Clock Input
23
26
Sub 6 ns
Any Micro⇔Cell
23
27 Add 4
ns
tCH + t CL(Note 2) 22
28
ns
NOTES: 1. Fast Slew Rate output available on Port C and F.
2. CLKIN tCLCL = tCH + tCL.
87
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