C164CL/SL データシートの表示（PDF） - Infineon Technologies

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C164CL/SL

16-Bit Single-Chip Microcontroller

Infineon Technologies 

C164CI/SI

C164CL/SL

A/D Converter Characteristics

(Operating Conditions apply)

Table 13 A/D Converter Characteristics

Parameter

Symbol

Limit Values

min.

max.

Unit Test

Conditions

Analog reference supply

VAREF SR 4.0

VDD + 0.1 V

1)

Analog reference ground

Analog input voltage range

Basic clock frequency

Conversion time

Calibration time after reset

Total unadjusted error

VAGNDSR VSS - 0.1

VAIN SR VAGND

fBC

0.5

tC CC –

tCAL CC –

TUE CC –

VSS + 0.2 V –

VAREF

V

2)

6.25

MHz 3)

40 tBC + –

tS + 2tCPU

3328 tBC –

±2

LSB

4)

tCPU = 1 / fCPU

5)

1)

Internal resistance of

reference voltage source

RAREF SR –

tBC / 60

- 0.25

kΩ tBC in [ns]6)7)

Internal resistance of analog RASRC SR –

source

tS / 450

- 0.25

kΩ tS in [ns]7)8)

ADC input capacitance

CAIN CC –

33

pF 7)

1) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages

within the defined voltage range.

If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV

specification) does not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be ±4 LSB.

2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in

these cases will be X000H or X3FFH, respectively.

3) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.

4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock tBC depend on programming and can be taken from Table 14.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5) During the reset calibration conversions can be executed (with the current accuracy). The time required for

these conversions is added to the total reset calibration time.

6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

7) Not 100% tested, guaranteed by design and characterization.

Data Sheet

55

V2.0, 2001-05

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