SC2450ISWTR(2001) データシートの表示（PDF） - Semtech Corporation

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SC2450ISWTR
(Rev.:2001)

BI-Phase/Dual Controller

Semtech Corporation 

SC2450

POWER MANAGEMENT

Control Loop Design (Cont.)

or

Step 1. Output filter corner frequency

R

1

.

Fo

2

.

F x_over

.

Vo

G pwm.V in.G error F esr

F o V bg

when

F esr< F o< F x_over

Fo = 1.453 KHz

Step 2. ESR zero frequency:

Fesr = 2.653 KHz

(5) The compensation capacitor is determined by choosing the

compensator zero to be about one fifth of the output filter cor-

ner frequency:

Fo

F zero 5

1

C 2 .π.R.F zero

(6) The final step is to generate the Bode plot, either by using

the simulation model in Fig. 1 or using the equations provided

here with Mathcad. The phase margin can then be checked

using the Bode plot. Usually, this design procedure ensures a

healthy phase margin.

Step 3. Check the following condition:

F

ers<

F

sw

5

Which is satisfied in this case.

Step 4. Choose crossover frequency and calculate compen-

sator R:

Fx_over = 30 KHz

R = 2.95 KΩ

Step 5. Calculate the compensator C:

An example is given below to demonstrate the procedure intro-

duced above. The parameters of the power supply are given

as:

V in := 24 V

C = 186 nF

Step 6. Generate Bode plot and check the phase margin. In

this case, the phase margin is about 85°C that ensures the

loop stability. Fig. 2 shows the bode plot of the loop.

V o := 2.5 V

I o := 20 A

F sw := 150 KHz

L := 4 µH

C o := 3000 µF

R c := 0.02 Ω

R 1 := 1.5 KΩ

R 2 := 1.0 KΩ

 2001 Semtech Corp.

17

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