ST62P10C-FASTROM データシートの表示（PDF） - STMicroelectronics

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ST62P10C-FASTROM

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

OPERATING CONDITIONS (Cont’d)

10.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fOSC, and TA.

Symbol

Parameter

Conditions

Min Typ 1) Max Unit

VIT+

VIT-

Vhys

VtPOR

tg(VDD)

Reset release threshold

(VDD rise)

Reset generation threshold

(VDD fall)

LVD voltage threshold hysteresis

VDD rise time rate 2)

Filtered glitch delay on VDD 3)

VIT+-VIT-

Not detected by the LVD

3.9

4.1

4.3

V

3.6

3.8

4

50

300 700 mV

mV/s

30

ns

Notes:

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.

2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

3. Data based on characterization results, not tested in production.

Figure 39. LVD Threshold Versus VDD and fOSC3)

FUNCTIONALITY

fOSC [MHz]

NOT GUARANTEED

DEVICE UNDER 8

RESET

IN THIS AREA 4

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

IN THIS AREA

FUNCTIONAL AREA

SUPPLY

0

2.5

3

3.5 VIT-≥3.6 4

4.5

5

VOLTAGE [V]

5.5

6

Figure 40. Typical LVD Thresholds Versus Figure 41. Typical LVD thresholds vs.

Temperature for OTP devices

Temperature for ROM devices

Thresholds [V]

4.2

4

VVIdTd+ up

3.8

VVIdTd- down

3.6

-40°C

25°C

95°C

T [°C]

125°C

Thresholds [V]

4.2

4

VVITd+d up

3.8

VVITd-d down

3.6

-40°C

25°C

95°C

T [°C]

125°C

65/104

1

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