ST72324J6B5 データシートの表示（PDF） - STMicroelectronics
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ST72324J6B5
STMicroelectronics
ST72324J6B5 Datasheet PDF : 161 Pages
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ST72324
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 43 on page
67). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 44 on page 67).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
6. The TAOC2HR, TAOC2LR registers are "write-
only" in Timer A. The corresponding event can-
not be generated (OCF2 is forced by hardware
to 0).
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 42. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
16-bit
16-bit
OC1R Register
OC2R Register
OC1E OC2E
OCIE
CC1 CC0
(Control Register 2) CR2
(Control Register 1) CR1
FOLV2 FOLV1 OLVL2
OLVL1
OCF1
OCF2 0
0
0
(Status Register) SR
Latch
1
Latch
2
OCMP1
Pin
OCMP2
Pin
66/161
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