ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
MOTOR SAMPLING CLOCK
(MSCR)
Read/Write
Reset Value: 0000 0000 (00h)
REGISTER
7
6
5
4
3
2
1
0
ZSV 0
0
0 SCF1 SCF0 ECM DISS
Bit 7 = ZSV Z Event Sampling Validation when
MOE bit is reset
This bit enables/disables Z event sampling in ei-
ther mode (sampling at PWM frequency or at fSCF
frequency selected by SCF[1:0] bits)
0: Z event sampling disabled
1: Z event sampling enabled
Bits 6:4 = Reserved, must be kept cleared.
Bits 3:2 = SCF[1:0] Sampling Clock Frequency
These bits select the sampling clock frequency
(fSCF) used to count D & Z events.
Table 82. Sampling Clock Frequency
SCF1
0
0
1
1
SCF0
0
1
0
1
fSCF
1 MHz (every 1µs)
500 kHz (every 2µs)
250 kHz (every 4µs)
125 kHz (every 8µs)
Note: Times are indicated for 4 MHz fPERIPH
Bit 1 = ECM: Encoder Capture Mode
This bit is used to select the source of events
which trigger the capture of the [MTIM:MTIML]
counter when using Encoder speed sensor (see
Figure 90).
0: Real-time Clock interrupts
1: Read access on MTIM register
Bit 0 = DISS Data Input Selection
This setting is effective only if PCN=0, TES=00
and SR=0.
0: Unused MCIx inputs are grounded
1: Unused MCIx inputs are put in HiZ
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