16-BIT TIMER (Cont’d)
Figure 48. Input Capture Block Diagram
ICAP1
pin
EDGE DETECT EDGE DETECT
ICIE
ICAP2
CIRCUIT2
CIRCUIT1
pin
IC2R Register
IC1R Register
ICF1
16-BIT
16-BIT FREE RUNNING
COUNTER
ST7MC1xx/ST7MC2xx
(Control Register 1) CR1
IEDG1
(Status Register) SR
ICF2
0
0
0
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 49. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
FF01
FF02
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: The active edge is the rising edge.
Note: The time between an event on the ICAPi pin
and the appearance of the corresponding flag is
from 2 to 3 CPU clock cycles. This depends on the
moment when the ICAP event happens relative to
the timer clock.
FF03
FF03
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