Z86E6116VSC(2008) データシートの表示（PDF） - Zilog

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Z86E6116VSC
(Rev.:2008)

CMOS Z8 16K/32K EPROM Microcontroller

Zilog 

Z86E61/E63

CMOS Z8 16K/32K EPROM Microcontroller

60

Table 32. Instruction Summary (Continued)

Instruction

and Operation

RP←src

STOP

SUB dst, src

dst←dst←src

SWAP dst

↓

7

07

0

↑

TCM dst, src

(NOT dst)

AND src

TM dst, src

dst AND src

XOR dst, src

dst←dst

XOR src

Address Mode

dst

src

Opcode

Flags Affected

Byte (Hex) C Z S V D H

Notea

6F

1-

-

-

-

-

2[ ]

[

[

[

[

1[

R

IR

Notea

F0

X*

*

X-

-

F1

6[ ]

-

*

*

0-

-

Notea

Notea

7[ ]

-

*

*

0-

-

B[ ]

-

*

*

0-

-

a. These instructions have an identical set of addressing modes, which are encoded for brevity. The first Op

Code nibble is found in the instruction set table above. The second nibble is expressed symbolically by a

’[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source)

is 13.

Address Mode

dst

src

r

r

r

Ir

R

R

R

IR

R

IM

IR

IM

Lower

Opcode Nibble

[2]

[3]

[4]

[5]

[6]

[7]

PS014401-1001

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