CS5532-ASZR データシートの表示（PDF） - Cirrus Logic
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CS5532-ASZR Datasheet PDF : 50 Pages
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3. PIN DESCRIPTIONS
CS5531/32/33/34-AS
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
AMPLIFIER CAPACITOR CONNECT
AMPLIFIER CAPACITOR CONNECT
POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER
LOGIC OUTPUT (ANALOG)/GUARD
LOGIC OUTPUT (ANALOG)
MASTER CLOCK
MASTER CLOCK
AIN1+ 1
20
AIN1-
C1
2
19
CS5531/2
3
18
C2 4
17
VA+ 5
16
VA- 6
15
A0 7
14
A1 8
13
OSC2 9
12
OSC1 10
11
AIN2+
AIN2-
VREF+
VREF-
DGND
VD+
CS
SDI
SDO
SCLK
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIGITAL GROUND
POSITIVE DIGITAL POWER
CHIP SELECT
SERIAL DATA INPUT
SERIAL DATA OUT
SERIAL CLOCK INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
AMPLIFIER CAPACITOR CONNECT
AMPLIFIER CAPACITOR CONNECT
POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER
LOGIC OUTPUT (ANALOG)/GUARD
LOGIC OUTPUT (ANALOG)
MASTER CLOCK
MASTER CLOCK
AIN1+
AIN1-
AIN4+
AIN4-
C1
C2
VA+
VA-
A0
A1
OSC2
OSC1
1
24
2
23
CS5533/4
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
AIN2+
AIN2-
AIN3+
AIN3-
VREF+
VREF-
DGND
VD+
CS
SDI
SDO
SCLK
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIGITAL GROUND
POSITIVE DIGITAL POWER
CHIP SELECT
SERIAL DATA INPUT
SERIAL DATA OUT
SERIAL CLOCK INPUT
Clock Generator
OSC1; OSC2 - Master Clock.
An inverting amplifier inside the chip is connected between these pins and can be used with a
crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible)
clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock
for the device.
Control Pins and Serial Data I/O
CS - Chip Select.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
44
DS289F5
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