ML6461CS データシートの表示（PDF） - Micro Linear Corporation
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ML6461CS Datasheet PDF : 30 Pages
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FUNCTIONAL DESCRIPTION (Continued)
selects between internal (B26=1) and external slave
modes (B26=0).
SELCCIR, B27 This bit determines the frequency of
choice between CCIR656 clock rate(27MHz) and Square
Pixel clock rate (24.54MHz). When this bit is set (B27=1),
CCIR656 clock rate is selected. When this bit is cleared
(B27=0), the Square Pixel clock rate is selected.
SLAVE_MODE, B26 This bit determines the choice of
two slave modes: internal slave mode or external slave
mode. In internal slave mode (B26=1), horizontal and
vertical timing information is embedded in the YCrCb
data (via SAV / EAV codes); while the HSYNC and
VSYNC pins can be used as outputs. In external slave
mode (B26=0), horizontal and vertical sync pulses must
ML6461
be provided for timing and synchronization;in this case
HSYNC and VSYNC pins are inputs. See Table 3.
HRESET_MODE, B25 This bit determines whether the
HSYNC is given at the beginning of active video (B25=1)
or HSYNC is given at the beginning of blanking (B25=0).
This bit (B25) is only available for external slave modes.
ANALOG_HBLANK, B24 This bit determines whether
the ML6461 is to encode for ITU_R656_compliant
"digital" or ITU_/SMPTE_compliant "analog" encoding
specifications. When this bit is cleared (B24=0), the
ML6461 is optimized for full "digital" line encoding,
where the number of active pixels is 720 for CCIR656
rates and 640 for square pixel rates. No tapering (edge
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 21
SYNC
LEVEL
10.003
±0.25µs
27.382µs
33.764µs
Closed Caption on Line21
[CC_21 = 1 and CC_284 = 0]
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 284
SYNC
LEVEL
10.003
±0.25µs
27.382µs
33.764µs
Closed Caption on Line284
[CC_21 = 0 and CC_284 = 1]
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A0 ~ A6 A7 A8 ~ A14 A15
R
T
LINE 21
50 ±2 IRE
10.5
±0.25µs
12.91µs
7 CYCLES
3.58MHz
COLOR
BURST
BLANK
LEVEL
40 IRE
TWO: 7 BIT + PARITY BIT
S
T
A A16 ~ A22 A23 A24 ~ A30 A31
R
T
LINE 284
SYNC
LEVEL
10.003
±0.25µs
27.382µs
SYNC
LEVEL
10.003
±0.25µs
33.764µs
27.382µs
Closed Caption on Line21 and Line 284
[CC_21 = 1 and CC_284 = 1]
Figure 13. Closed Caption on Line 21 and Line 284.
33.764µs
19
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