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XR8051ASO8X データシートの表示(PDF) - Exar Corporation

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XR8051ASO8X
Exar
Exar Corporation 
XR8051ASO8X Datasheet PDF : 24 Pages
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Data Sheet
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response.
Evaluation Board #
Products
CEB006
XR8052 in SOIC
CEB010
XR8052 in MSOP
CEB018
XR8054 in SOIC
CL (Pf)
22pF
47pF
100pF
492pF
Rs (Ω)
0
15
15
6.5
-3db BW (MHz)
120
80
65
40
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 10-18. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Figure 8. CEB002 & CEB003 Schematic
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
Products
CEB002
XR8051 in SOT23
CEB003
XR8051 in SOIC
©2013 Exar Corporation
19/23
Rev 1A

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