STM32F215RET6 データシートの表示（PDF） - STMicroelectronics

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STM32F215RET6

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Revision history

STM32F21xxx

Table 92. Document revision history (continued)

Date

Revision

Changes

20-Dec-2011

Updated SDIO register addresses in Figure 13: Memory map.

Updated Figure 3: Compatible board design between STM32F10xx

and STM32F2xx for LQFP144 package, Figure 2: Compatible board

design between STM32F10xx and STM32F2xx for LQFP100 package,

Figure 1: Compatible board design between STM32F10xx and

STM32F2xx for LQFP64 package, and added Figure 4: Compatible

board design between STM32F10xx and STM32F2xx for LQFP176

package.

Updated Section 2.2.3: Memory protection unit.

Updated Section 2.2.6: Embedded SRAM.

Updated Section 2.2.28: Universal serial bus on-the-go full-speed

(OTG_FS) to remove external FS OTG PHY support.

In Table 5: STM32F21x pin and ball definitions: changed SPI2_MCK

and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added

ETH _RMII_TX_EN alternate function to PG11. Added EVENTOUT in

the list of alternate functions for I/O pin/balls. Removed

OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate

functions.

In Table 7: Alternate function mapping: changed I2S3_SCK to

I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for

PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA,

OTG_FS_SCL and OTG_FS_INTN alternate functions. Updated

peripherals corresponding to AF12.

6

Removed CEXT and ESR from Table 11: General operating

conditions.

Added maximum power consumption at TA=25 °C in Table 20: Typical

and maximum current consumptions in Stop mode.

Added CRYPTO, RNG, and HASH consumption in Table 23:

Peripheral current consumption.

Updated md minimum value in Table 33: SSCG parameters constraint.

Added examples in Section 5.3.11: PLL spread spectrum clock

generation (SSCG) characteristics.

Updated Table 51: SPI characteristics and Table 52: I2S

characteristics.

Updated Figure 44: ULPI timing diagram and Table 58: ULPI timing.

Updated Table 60: Dynamics characteristics: Ethernet MAC signals for

SMI, Table 61: Dynamics characteristics: Ethernet MAC signals for

RMII, and Table 62: Dynamics characteristics: Ethernet MAC signals

for MII.

Updated maximum fS values in Table 63: ADC characteristics.

Section 5.3.25: FSMC characteristics: updated Table 69 toTable 80,

changed CL value to 30 pF, and modified FSMC configuration for

asynchronous timings and waveforms. Updated Figure 58:

Synchronous multiplexed PSRAM write timings.

UpdatedTable 81: DCMI characteristics.

Updated Table 88: UFBGA176+25 - ultra thin fine pitch ball grid array

10 × 10 × 0.6 mm mechanical data.

168/173

Doc ID 17050 Rev 8

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