LFSCM3GA115EP1-5FC1704C データシートの表示（PDF） - Lattice Semiconductor

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LFSCM3GA115EP1-5FC1704C

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeSC/M Family Data Sheet

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the low-to-high transition of the reset, as shown in Figure 2-16.

Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM, FIFO and shift register implementations. For the EBR FIFO mode,

the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-16. The

reset timing rules apply to the RPReset input vs. the RE input and the RST input vs. the WE and RE inputs. Both

RST and RPReset are always asynchronous EBR inputs. For the EBR shift register mode, the GSR signal is

always enabled and the local RESET pin is always asynchronous.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

For more information about on-chip memory, see TN1094, On-Chip Memory Usage Guide for LatticeSC Devices.

Programmable I/O Cells (PIC)

Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to

the PADs as shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal

(TO) to PURESPEED I/O buffer, and receives input (DI) from the buffer. The PIO contains advanced capabilities to

allow the support of speeds up to 2Gbps. These include dedicated shift and DDR logic and adaptive input logic.

The dedicated resources simplify the design of robust interfaces.

2-15

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