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STM32F051K6T7 データシートの表示(PDF) - STMicroelectronics

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STM32F051K6T7 Datasheet PDF : 122 Pages
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Electrical characteristics
STM32F051x4 STM32F051x6 STM32F051x8
6.3.17 DAC electrical specifications
Table 55. DAC characteristics
Symbol
Parameter
Min Typ
Max
Unit
Comments
VDDA
Analog supply voltage for
DAC ON
2.4
-
3.6
V
-
RLOAD(1)
Resistive load with buffer
ON
RO(1)
Impedance output with
buffer OFF
5
-
25
-
-
-
-
kLoad connected to VSSA
-
kLoad connected to VDDA
When the buffer is OFF, the
15
k
Minimum resistive load between
DAC_OUT and VSS to have a
1% accuracy is 1.5 M
CLOAD(1) Capacitive load
-
-
Maximum capacitive load at
50
pF DAC_OUT pin (when the buffer
is ON).
DAC_OUT Lower DAC_OUT voltage
min(1) with buffer ON
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer ON
DAC_OUT Lower DAC_OUT voltage
min(1) with buffer OFF
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer OFF
It gives the maximum output
0.2
-
-
V excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
-
-
VDDA – 0.2
V
VDDA = 3.6 V and (0x155) and
(0xEAB) at VDDA = 2.4 V
-
0.5
-
mV
It gives the maximum output
excursion of the DAC.
-
- VDDA – 1LSB V
IDDA(1)
DAC DC current
consumption in quiescent
mode(2)
-
-
-
-
600
µA
With no load, middle code
(0x800) on the input
700
µA
With no load, worst code
(0xF1C) on the input
DNL(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
-
-
Integral non linearity
(difference between
-
-
INL(3)
measured value at Code i
and the value at Code i on a
line drawn between Code 0
-
-
and last Code 1023)
Offset error
-
-
(difference between
Offset(3) measured value at Code
-
-
(0x800) and the ideal value
= VDDA/2)
-
-
±0.5
LSB
Given for the DAC in 10-bit
configuration
±2
LSB
Given for the DAC in 12-bit
configuration
±1
LSB
Given for the DAC in 10-bit
configuration
±4
LSB
Given for the DAC in 12-bit
configuration
±10
mV
-
±3
LSB
Given for the DAC in 10-bit at
VDDA = 3.6 V
±12
LSB
Given for the DAC in 12-bit at
VDDA = 3.6 V
80/122
DocID022265 Rev 7

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