STM8S105S4(2015) データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
STM8S105S4
(Rev.:2015)
(Rev.:2015)
STMicroelectronics
STM8S105S4 Datasheet PDF : 121 Pages
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Option byte
8
Option byte
STM8S105x4/6
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option byte can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Addr.
Option
name
Option
byte
no.
7
Table 11. Option byte
Option bits
6
5
4
3
2
0x4800
0x4801
0x4802
0x4803
0x4804
Read-out
protection
(ROP)
User boot
code (UBC)
Alternate
function
remapping
(AFR)
OPT0
ROP [7:0]
OPT1
NOPT1
OPT2
AFR7
AFR6
AFR5
UBC [7:0]
NUBC [7:0]
AFR4
AFR3
NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3
AFR2
NAFR2
0x4805h
0x4806
Misc. option
OPT3
NOPT3
Reserved
Reserved
HSI
TRIM
NHSI
TRIM
LSI _ EN
IWDG
_HW
NLSI
_ EN
NIWDG
_HW
0x4807
0x4808
Clock option
OPT4
NOPT4
Reserved
Reserved
CKAWU
EXT CLK
SEL
NEXT
CLK
NCKA
WUSEL
0x4809
0x480A
0x480B
0x480C
0x480D
0x480E
HSE clock
startup
Reserved
Reserved
OPT5
NOPT5
OPT6
NOPT6
OPT7
NOPT7
HSECNT [7:0]
NHSECNT [7:0]
Reserved
Reserved
Reserved
Reserved
0x480F
-
Reserved
0x48FD
-
Reserved
Reserved
1
AFR1
NAFR1
WWDG
_HW
NWWDG
_HW
PRS C1
NPRSC1
Factory
default
0
setting
0x00
AFR0
0x00
0xFF
0x00
NAFR0
0xFF
WWDG
_HALT
NWWG
_HALT
PRS C0
0x00
0xFF
0x00
NPR SC0
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
-
-
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